1. Field of the Invention
The present invention relates to a method for laminating a circuit pattern tape over a wafer, and more particularly to a method for efficiently laminating a circuit pattern tape over a wafer formed with a plurality of semiconductor chip units by means of an elastomeric adhesive tape while maintaining an accuracy in position and orientation.
2. Description of the Prior Art
In pace with the recent trend of electronic appliances, such as electronic products for domestic and official purposes, communication appliances, and computers, toward a compactness and high performance, semiconductor packages, which are used for such electronic appliances, have been required to have a compact, highly multi-pinned, light, simple structure while having a high performance.
Such a requirement for semiconductor packages has resulted in developments of semiconductor packages having a size identical or similar to the size of a semiconductor chip packaged therein. Such a semiconductor package is called a xe2x80x9cchip size (or scale) semiconductor packagexe2x80x9d or a xe2x80x9cchip-on-boardxe2x80x9d semiconductor package. Currently, the demand of semiconductor packages having such a structure is increased. Chip size semiconductor packages are fabricated by laminating a circuit pattern tape formed with a plurality of circuit pattern units over a wafer formed with a plurality of semiconductor chip units, carrying out a well-known packaging process involving a wire bonding process for electrically connecting the circuit patterns of the circuit pattern tape to the die pads of the semiconductor chips in the wafer, a resin molding process for encapsulating the wire bonding areas of the wafer with an encapsulate resin, and a process for attaching solder balls, as external input/output terminals, to the wafer, and finally conducting a singulation process for separating the resultant wafer into individual semiconductor chips, that is, individual independent semiconductor packages.
The most important process in the fabrication of semiconductor packages as mentioned above is a process for laminating a circuit pattern tape, which is formed with an adhesive layer, over a wafer while maintaining desired relative positional and directional relations between the circuit pattern tape and wafer. When the circuit pattern tape is bonded to the wafer by means of the adhesive layer while maintaining an accuracy in position and orientation, bond fingers formed on the circuit pattern tape and input/output pads formed on the semiconductor chips of the wafer are exposed through associated openings provided at the circuit pattern tape, so that they can be electrically connected together in accordance with a wire bonding process. However, where the circuit pattern tape is laminated over the wafer without maintaining an accuracy in position and orientation, a part of or all of the input/output pads on each semiconductor chip cannot be wire-bonded because of a possible shielding thereof by the circuit pattern tape or because of a possible deviation in the wire length required for the wire bonding between the associated bond finger and die pad due to an inaccurate lamination angle. In severe cases, portions of the circuit pattern tape, where circuit patterns are formed, or a part of the semiconductor chips may be cut in a singulation process which is conducted to individually separate packages from the wafer laminated with the circuit pattern tape. As a result, a degradation in the yield of semiconductor packages occurs.
FIG. 28A is a plan view illustrating a circuit pattern tape used in a conventional lamination method. In FIG. 28A, the circuit pattern tape is denoted by the reference numeral 10xe2x80x2. FIG. 28B is an enlarged view illustrating a portion D in FIG. 28A. FIG. 28C is a cross-sectional view taken along the line Ixe2x80x94I of FIG. 28A. Now, the circuit pattern tape will be described in conjunction with FIGS. 28A to 28C.
A plurality of circuit pattern units 11xe2x80x2 are formed at a portion of the circuit pattern tape corresponding to a wafer (denoted by the reference numeral 2 in FIG. 2A). Each circuit pattern unit 11xe2x80x2 has an independent circuit pattern. A cover coat 19 is coated over the portion of the circuit pattern tape, where the circuit pattern units 4 are formed, corresponding to the wafer.
FIG. 28B, which is an enlarged view illustrating the portion D of FIG. 28A, shows four circuit pattern units 11xe2x80x2 adjoining together. In FIG. 28B, the reference numeral 12 denotes conductive traces. Each conductive trace 12 is not coated with the cover coat 19 at its one end. The end of each conductive trace 12 not coated with the cover coat 19 is connected to a solder ball land 13 attached with a solder ball (not shown). Each conductive trace 12 is also connected at the other end thereof to an associated one of bond fingers formed at an associated one of bond finger formation regions 15. A plurality of such conductive traces 12 form the circuit pattern of each circuit pattern unit 11. Bond finger formation regions 15 are not coated with the cover coat 19, so that bond fingers 14 thereof are outwardly exposed, similarly to the solder ball lands 13. An opening formation region is defined within each bond finger formation region 15. Such opening formation regions are removed in accordance with a punching process prior to a lamination of the circuit pattern tape 10xe2x80x2 over the wafer 2 formed with a plurality of semiconductor chip units (denoted by the reference numeral 3 in FIG. 2A), thereby forming openings 16. Die pads (denoted by the reference numeral 4 in FIG. 2B) on each semiconductor chip unit (denoted by the reference numeral 3 in FIG. 2B) are upwardly exposed through an associated one of the openings 16. The exposed die pads are coupled to bond fingers 14 by means of conductive wires (not shown), respectively. In FIG. 28B, the reference numeral 17 denotes bus lines. The bus lines 17 are needed to achieve a formation of a nickel (Ni)/platinum (Au) coating for an easy attachment of solder balls (not shown) to the solder ball lands 13 or to achieve an electrolytic or electroless plating allowing a formation of a platinum (Au) or silver (Ag) coating required to achieve an easy bonding of wires (not shown) to the bond fingers 14. The bus lines 17 should be removed in order to prevent the conductive traces 12 from being conducted together by those bus lines 17 after the wafer is separated into individual packaged semiconductor chip units as it is cut along singulation lines 20.
FIG. 28C illustrates a cross-sectional structure of the circuit pattern tape 10xe2x80x2 for semiconductor packages which is used in the conventional lamination method. The lowermost layer of the structure shown in FIG. 28C is an insulating polymide layer 18. Conductive traces 12 and solder ball lands 13 are formed on the polyimide layer 18. Bond fingers 14 are also formed on the polyimide layer 18 around respective openings 16. The cover coat 19 is laminated over the conductive traces 12. The solder ball lands 13 and bond fingers 14 are not covered with the cover coat 19, so that they are upwardly exposed. At the peripheral region of each circuit pattern unit 11xe2x80x2, a conductive metal thin film 12xe2x80x2 is laminated over the polyimide layer 18. The cover coat 19 is also laminated over the conductive metal thin film 12xe2x80x2.
In a lamination process according to the conventional lamination method, the circuit pattern tape formed with the adhesive layer is pressed onto the wafer laid on a die, for its bonding to the wafer, while aligning a reference position of the circuit pattern tape with a reference position of the wafer. However, the alignment between the reference positions of the circuit pattern tape and wafer is manually conducted after the alignment state is identified by the naked eye of the operator. For this reason, there is a high possibility of an inaccurate lamination in terms of position and orientation. Moreover, a lot of time is taken for the lamination process. As a result, a degradation in productivity and yield occurs.
The circuit pattern tape 10xe2x80x2, which is used in the conventional lamination method, involves a non-uniform distribution of the conductive metal forming the circuit pattern. For this reason, when the lamination process is carried out at a high temperature, there is a problem in that voids may easily be formed in the circuit pattern tape 10xe2x80x2 due to a relatively high difference in regard to the coefficient of thermal expansion between the conductive metal and the resin material of the polyimide layer 18 or cover coat 19.
Moreover, a bowing phenomenon may easily occur at the wafer 2 when the wafer 2 laminated with the circuit pattern tape 10xe2x80x2 in accordance with the lamination process conducted at a high temperature is maintained at room temperature. This results from the relatively great difference in regard to the coefficient of thermal expansion between the conductive metal and the resin material of the polyimide layer 18 or cover coat 19. Such a bowing phenomenon may become severe where the circuit pattern tape 10xe2x80x2 having the above mentioned structure is used. This is because the circuit pattern tape 10xe2x80x2 has the planar conductive metal thin film 12xe2x80x2 which has a large area and is interposed between the polyimide layer 18 and cover coat 19. In the manufacture of semiconductor packages, such a bowing phenomenon serves to make it difficult to attach the circuit pattern tape 10xe2x80x2 to the wafer in an accurate horizontal state. Furthermore, this bowing phenomenon makes it difficult to achieve smooth subsequent processes. As a result, degraded semiconductor packages may be produced.
Therefore, an object of the invention is to provide a method for efficiently laminating a circuit pattern tape over a wafer formed with a plurality of semiconductor chip units by means of an elastomeric adhesive tape while maintaining an accuracy in position and orientation.
Another object of the invention is to provide a lamination method capable of effectively preventing or inhibiting the formation of voids in a process for laminating a circuit pattern tape over a wafer.
Another object of the invention is to provide a lamination method capable of preventing a bowing phenomenon occurring in a lamination process carried out at a high temperature or in a subsequent process.
In accordance with one aspect, the present invention provides a method for laminating a circuit pattern tape over a wafer, comprising the steps of: preparing a circuit pattern tape formed with an adhesive layer, along with a wafer; detecting at least one reference position of the prepared circuit pattern tape and at least one reference position of the prepared wafer using visual detecting means; outputting results obtained at the detecting step in the form of visual images capable of allowing a comparison of the detection results; carrying out a reference position correction involving movements of the wafer in an X-axis and/or a Y-axis direction and/or by a desired angle, thereby allowing the reference position of the circuit pattern tape and the reference position of the wafer to correspond to each other; and laminating the circuit pattern tape over the wafer when the reference positions correspond to each other.
In accordance with another aspect, the present invention provides a method for laminating a circuit pattern tape over a wafer, comprising: an adhesive layer-carrying circuit pattern tape and wafer preparing step for feeding an adhesive layer-carrying circuit pattern tape in a sucked state by a vacuum sucking tool included in a circuit pattern tape sucking/feeding assembly while sucking and holding a wafer on a die arranged beneath the sucking tool by a wafer sucking/holding assembly; a reference position detecting step for detecting at least one reference position of the adhesive layer-carrying circuit pattern tape and at least one reference position of the wafer by visual detecting means included in a visual detecting assembly; a reference position correcting step for comparing the detection results outputted from the visual detecting assembly with each other, determining whether or not the compared reference positions correspond to each other, based on the comparison results, and, if the compared reference positions do not correspond to each other, then shifting the die holding the wafer in an X and/or a Y-axis direction or by a desired angle until the reference positions correspond to each other; and if the compared reference positions correspond to each other, then downwardly feeding the adhesive layer-carrying circuit pattern tape sucked onto the sucking tool to the wafer held on the die, thereby laminating the adhesive layer-carrying circuit pattern tape over the wafer.